Technical Field
The present disclosure relates to integrated circuits (ICs) incorporating semiconductor materials, and more specifically, to IC structures which includes a pair of metal fins and methods of forming the same. Each metal fin can be a unitary structure which functions as both a metal wire and a via during operation, and processes of forming the pair of metal fins can reduce a lateral separation distance between metal wires and vias in an IC.
Related Art
Each IC can be made up of billions of interconnected devices, such as transistors, resistors, capacitors, and diodes, located on one or more chips of semiconductor substrate material. The quality and viability of a product including an IC can be at least partially dependent on the techniques used for fabricating the IC and the structure of various components therein. Fabrication of an IC can include two phases: front-end-of-line processes (FEOL) and back-end-of-line processes (BEOL). FEOL generally includes fabrication processes performed on a wafer up to and including the formation of a first “metal level,” i.e., a metal wire for connecting several semiconductor devices together. BEOL generally includes fabrication processes following the formation of the first metal level, including the formation of all subsequent metal levels. Each metal level can include metal wires therein, which can be connected to other metal levels through vertically-oriented conducting wires known as vias. In conventional BEOL processing, a layer of vias is formed to connected devices in an IC structure to a layer of metal wires formed on top of the vias, with a successive layer of vias formed thereon, followed by another layer of meal wires, etc. To provide greater scaling and sophistication of the fabricated device, the number of metal levels can be varied to suit a particular application, e.g., by providing four to six metal levels, or as many as, in a further example, sixteen or more metal levels. Among other physical characteristics, the specific methodologies used during BEOL can define a resulting “pitch” of components in the IC.
Pitch is a quantity which measures the periodic distance of two features. A value of pitch specifies a sum of the width of a feature (e.g., a transistor gate) and the space on one side of the feature separating that feature from a neighboring feature. Depending on the photolithographic process being used, factors such as optics and wavelengths of light or radiation restrict how small the pitch can be before features can no longer be reliably printed to a wafer or mask. As such, the pitch limits the smallest size of any features that can be created on a wafer. Various changes and improvements to IC fabrication, over time, have accommodated progressive reductions in pitch to provide greater component densities and greater operational sophistication in an IC product.